1. Field of the Invention
The present invention relates to an error correction apparatus for correcting erroneous image data and a solid state image capturing apparatus using the error correction apparatus.
2. Description of the Prior Art
When data error caused in the course of capturing, processing and transmitting are included in the image data of Audio-Video apparatus, such as a VCR, video disk, scanner and camera, the quality of the displayed picture will be deformed seriously. Especially, when defects are in the image capturing device, the captured image data always include the error data at the same corresponding pixel. Consequently, the quality of the displayed picture is always deformed seriously.
Recently, a solid state image capturing device, especially CCD (Charge Coupled Device) is widely used as an image capturing device. As is often the case with CCD, defective pixels resulting from the manufacturing process appear in the finished product. Because of the difficulty and complex integrity of CCD device manufacturing, a perfectly finished device without defective pixels is hard to obtain and it is difficult to raise the product ratio. Consequently, it is widely seen that error correction apparatus is added to a defect-containing CCD to correct erroneous data corresponding to the defective pixels and to make the CCD a useful finished product.
A conventional error correction apparatus is disclosed in the Japanese laid-open application JP58-68378. Error generated by defective pixels in each CCD is corrected by an error correction apparatus corresponding to each CCD. FIG. 29 is a schematic diagram showing a configuration of the conventional error correction apparatus.
In FIG. 29, there are an input node 70 into which digital output data converted from CCD capturing data are input (here the input digital data are digitized by each period for one pixel because CCD outputs data by each pixel), D (Delay) flip-flops 72 and 73 for delaying a period of one pixel, an adder 74, and a shift resistor 75 for shifting an input signal for one bit and reducing the output data to one-half the value of the input signal. An error correction circuit 71 is configured of the above elements. Besides the error correction circuit 71, there are an output node 82 for outputting signals delayed one period of pixel from the signal inputted by the input node 70, an output node 83 for outputting corrected signal outputted from the error correction circuit 71, a selector 76 for outputting one of the signals selected from the signals appearing on output node 82 or 83, and an output node 77 of the error correction apparatus. In addition, there are a controller 78 outputs control signal C, a comparator (CMP) 19, a ROM (Read-Only Memory) 81 for recording the information of coordinates of the defective pixels, and a timing generator (T.G.) for generating required clock for driving CCD.
The above-mentioned conventional error correction apparatus works as follows;
First, as for the function of error correction circuit 71, a digital signal from input node 70 is delayed one period of pixel and inputted to output node 82. The mean value of the data of before and after the data output from 82 is outputted as corrected data to output node 83.
Next, as for the function of controller 78, T.G. 14 outputs coordinates (h, v) of a data which is being inputted to one input node 82 to the comparator 19 as an address signal. The coordinates (x, y) of a defective pixel to be corrected are inputted to the other input node of the comparator 19 as a defective pixel address signal from the ROM 81. Consequently, control signal C, which has high level when erroneous data appears at output node 82, is output from the comparator 19.
The selector 76 normally selects the signal outputted from the output node 82 and it selects the corrected data inputted from output node 83 when control signal C is at a high level. Consequently, erroneous data are replaced with corrected data one after another. Thus, the next coordinates of erroneous data are outputted from the ROM 81 to the comparator 19 after completion of the previous erroneous data replacing process and all erroneous data are replaced with corrected data.
The above-mentioned error correction apparatus only can work well when surrounding data are low frequency data as shown in FIG. 30(a). When the surrounding data are high frequency data, erroneous data are not corrected to appropriate data as shown in FIG. 30(b). This margin of error in the correction process becomes noise and it deforms the quality of display images. Therefore, a solid state capturing device that is free or nearly free from defects is required for VCR in order to avoid deformation. However, it is quite difficult to achieve high production ratio for digital high quality vision VCR because of its large scale of integrated pixels and this problem increases the cost for such VCR.